1. Field of the Invention
This invention relates to field effect transistor logic circuits and more particularly to a high speed and low power enhancement/depletion mode FET logic circuit.
2. Description of the Prior Art
FET logic circuits employing both depletion mode and enhancement mode field effect transistors are well known in the art. For example, the NOR circuit illustrated in FIG. 1 includes a plurality of parallel connected enhancement mode devices such as TA and TB and a depletion mode load FET TC. An up level input signal on any of the input nodes will produce a down level output signal. When all the input nodes are maintained at a down level, the output node will charge to an up level. A known advantage of the self-biased depletion mode FET load device TC is that the output node is permitted to charge to a full up level provided by the positive supply potential. A more detailed description of this prior art circuit is found, for example, in Proebsting U.S. Pat. No. 3,775,693.
A problem with the above described logic circuit is that the internal logic nodes must switch from 0 volts to +5 volts and vice versa (a 5 volt logic swing) in order to propagate binary logic information. Typically, hundreds of such logic circuits may be placed on a single semiconductor chip. Such FET circuits are known to have relatively high load capacitances as illustrated by capacitance CL in FIG. 1 which must be charged and discharged during each switching transition. Each of the field effect transistors within the circuit has a finite transconductance in its on state which, together with the load capacitance, forms an RC circuit. It is known to increase the transconductance of field effect transistors for the purpose of reducing the RC time constant and thereby to increase the switching speed of the circuit. Unfortunately, field effect transistors with a higher transconductance also consume larger amounts of power and usually occupy more space on the semiconductor surface, both the aforementioned characteristics being highly undesirable.
Also known in the prior art are other applications for depletion/enhancement mode field effect transistors as illustrated in the above named IBM TDB to Freeman et al. Such circuits are required for converting potential levels compatible with bipolar logic levels to field effect transistor logic levels. The circuit from the Freeman et al TDB is reproduced as prior art FIG. 2. As illustrated, the circuit accepts an input logic swing of from 0 to +3 volts and provides an output logic swing of from 0.5 to +8.5 volts. The circuit includes enhancement mode device TE and depletion mode devices TD, TF, and TG. The input is received at the source of grounded gate device TD and is provided to the gate electrode of enhancement mode device TE which acts as an inverter with self-biased depletion mode load device TG.
A circuit quite similar to that described in the aforementioned Freeman et al. TDB is also illustrated in the above named Askin et al. TDB. The IBM TDB to Askin et al describes a level converting circuit including two depletion mode field effect transistors corresponding to devices TD and TF in the Freeman et al. TDB. In the Askin et al. circuit, specific width to length ratios and threshold voltage levels are disclosed and the supply and input potential levels are different. Otherwise, the circuits in the two TDB's perform the same function and both provide output logic swings substantially equal to the difference of the applied supply potentials. Since the output logic voltage swings described in all of the aforementioned prior art (both FIG. 1 and FIG. 2) are substantially equal to the full supply potential, power dissipation and logic switching times are presumed to be comparable.